The present invention relates generally to a dynamic random access memory (DRAM) device and, more particularly, to a vertical DRAM device having robust gate-to-storage node isolation.
In the semiconductor industry, there is an ever-increasing desire to increase memory density and performance. These goals are often achieved by scaling dynamic random access memory (DRAM) devices to smaller dimensions and operating voltages.
A DRAM cell may include a horizontal, planar, MOSFET (metal oxide semiconductor field effect transistor) transfer device coupled to a deep trench storage capacitor by a buried strap. As the size of such a DRAM cell is scaled to increase memory density, scaling of the channel length of the transfer device may be limited to prevent degradation of sub-threshold leakage requirements (or retention time requirements).
Vertical memory devices, which use a trench to form both a signal storage node and a signal transfer device, have been proposed to increase memory density. Vertical memory devices may have degrading performance because of reduced storage capacitance, when a nitride is used as a node dielectric material in a vertical memory device having very small dimensionsxe2x80x94eg, below 0.12 micron design trench DRAM.
Also, heavily doped polysilicon which has been used for a node conductor does not operate satisfactorily in below 0.12 micron design trench DRAMS, because of, eg, its high electrical resistance and the carrier depletion from the doped polysilicon.
To overcome the shortcomings of conventional DRAM devices, a new DRAM device is provided. A principal object of the present invention is to provide a DRAM device that has improved charge retention characteristicsxe2x80x94while retaining a nitride as the node dielectric.
A related object is to provide a process of manufacturing such a DRAM device.
Another subject is to provide a process of manufacturing such a DRAM device which is compatible with manufacturing support circuitry.
To achieve these and other objects, the present invention provides a dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. The storage node conductor comprises a metal or a metal alloy such as tungsten, WN, TiN or a metal silicide. Preferably, the DRAM device has a width dimension (W) of less than 0.12 microns, and an aspect ratio (D/W) of greater than 50.